Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.
Trends in portable electronic device design exacerbate the problem of limited available power. First, device form factors tend to shrink, due to increasing integration of electronics and miniaturization of component parts, such as disk drives. This forces the size of the battery to shrink as well, which generally reduces the available energy storage capacity. Second, electronic devices are increasingly sophisticated, offering new applications, more sophisticated user interfaces, enhancements such as encryption, and the like. The additional software implementing these features requires increased computational power to execute, which translates to larger, or additional, processors and more memory. Finally, successive generations of portable electronic device often add additional features such as various modes of wireless connectivity, which may require the integration of additional chip sets and other electronics. An increase in the demand for power by more processors and circuits, coupled with ever-shrinking battery size and capacity, has made power management a critical area of optimization for portable electronic device designers.
Several approaches to power management are known in the art. One such approach is to identify circuits (or sub-circuits) that are not used for extended periods, and put them into a low-activity state, also referred to as a “sleep mode,” even if other circuits in the device are fully active. As one example, the illuminated display screen of many devices will shut off after a (selectable) duration of no user interactivity. One way to shut down digital circuits is to isolate clocks signals from these circuits. Since storage elements within the digital circuits only change state in response to clock signal edges or levels, power-consuming electrical activity within the circuits effectively ceases.
Another approach to power management is to selectively provide operating power to various circuits (or sub-circuits) only as it is required. This selective power supply approach is possible by dedicating switched mode power supplies to each circuit. As well known in the art, a switched mode power supply transfers discrete quanta of charge from a power source (such as a battery) into a power storage and integration device (such as an inductor or capacitor), from which the power is made available to the circuit. By disabling the clocking signal used by a switched mode power supply, the circuits served by the power supply are rendered non-operative until the clock is again enabled and the power supply again begins switching charge from the power source to the load.
Even when several discrete circuits of a portable electronic device are simultaneously active, it may be advantageous to balance the current drain from the battery over time—that is, reduce or eliminate current “surges” caused by simultaneous clocking of digital electronics in several independent circuits, and/or the simultaneous switching of charge from the battery by numerous power supplies. One way to achieve such balance is by staggering the relative phases of the clock signals distributed to the disparate circuits or power supplies.
A clock generation and management approach that provides flexibility in clock enablement and relative phase for a plurality of discrete clock signals would be beneficial in power management for modern portable electronic devices. However, known clock management circuits lose phase synchronization between multiple clocks when one or more of the clock signals is disabled, and later enabled.
FIG. 1 depicts a reference clock signal Clk_in, and three output clock signals, each having a predetermined phase shift relative to each other. FIG. 1 also depicts a clock enable signal for the first output clock signal (other clocks are continuously enabled). During a first duration of output signal Clk1_phase_shifted being enabled, beginning at time t1, the three output clock signals have the phase shifts, referenced to the first clock signal, as indicated in the second column of the table. That is, the second clock has a delay offset from the first clock by π/2, or 90°, and the third clock has a delay offset from the first clock by π, or 180° (that is, opposite phase). At time t2, the first output clock signal is disabled, effectively placing a circuit or switched mode power supply in a “sleep” mode. When the circuit or power supply is again required to be active, the first clock is again enabled at time t3, and begins oscillating at time t4. However, the re-enabled first clock is shifted in phase, relative to its prior operation, by π, or 180° (the phase shift listed in the table of FIG. 1 for the first output clock is 0 because it is the reference position—the table lists phase changes relative to the first output clock). This shift in the first clock's phase (relative to its earlier phase) alters the phase relationship of the other two clocks relative to the first clock. The second clock now has a leading offset from the first clock of pi/2, or 90°, rather than a trailing phase shift, and the third clock has no phase shift relative to the first clock. Because the relative phases of the clocks signals are different after re-enabling the first clock signal, the carefully designed balance of instantaneous loads on the power source, such as a battery, will be upset, resulting in sub-optimal operation (e.g., reduced battery life, increased instantaneous current and higher heat dissipation, etc.).
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.